1. Field of the Invention
The present invention relates to package design for integrated circuits (ICs), and in particular relates to methods and apparatuses for providing packages which efficiently connect an integrated circuit die to a printed circuit board (PCB).
2. Description of the Related Art
As ICs include a larger number of circuits, use larger silicon areas, and operate at increasingly higher clock frequencies, surface-mounted packages for ICs are correspondingly required to have increasingly higher lead counts, smaller footprints and higher electrical and thermal performance, while at the same time achieving at least existing accepted reliability standards. Conventional TAB- or lead frame-based packages can deliver satisfactory thermal and electrical performance up to about 300 leads, at 10 watts, and operate up to 50 MHz. However, as the lead count increases above 300 leads, to avoid an increase in the footprint, the lead pitch (i.e. spacing between leads) is required to be less than 0.5 mm. A larger footprint would prevent high density board assembly, which is critical for many products, particularly in portable and consumer oriented products, where function in limited space is an important competitive advantage. Conversely, a fine lead pitch requires expensive placement equipment and a difficult assembly process. In addition, from the product design point of view, to accommodate fine pitch packages, PCBs are required to have more signal layers and more vias. These factors lead to lower yield in the assembly process and higher cost for PCBs.
In response to the demand for IC packages of higher lead count and smaller foot print, Ball Grid Array (BGA) packages are developed. A BGA package eliminates the need for fine pitch and reduces package footprint. A BGA package is a surface-mount package that is assembled to the external or "mother" PCB using an area array of solder balls, instead of fine pitch in-line leads which are easily damaged during the process of installing the IC on an external PCB. An advantage of the BGA package is a small footprint, a large ball grid array pitch and a relatively simple, almost self-aligning, assembly process to the external PCB. For example, a 208 lead, 2 mm thick QFP (Quad Flat Pack) has a typical footprint of 32.times.32 mm and a 0.5 mm lead pitch. In contrast, a 212-pin BGA package would be 1.5 mm thick and has a footprint of 27.times.27 mm, using a 1.5 mm ball pitch. At the minimum, a BGA package requires a two-metal layer PCB substrate instead of a lead frame or TAB. Such BGA package is typically a "cavity up" package, which is assembled with the back of the semiconductor die attached to the top surface (i.e. the upward-facing surface) of the substrate. A typical substrate is a PCB. The die is wire-bonded to the substrate traces and overmolded. When assembled to an external PCB, an area array of solder balls is attached to the exposed back-side (i.e. the downward-facing surface of the substrate) metal traces of the substrate routed from the top surface.
An example of a BGA package is described in U.S. Pat. No. 5,136,366, entitled "Overmolded Semiconductor Package With Anchoring Means", issued Aug. 4, 1992 to Motorola, Inc. The main limitations of prior art BGA packages are their low power dissipation, limited electrical performance and susceptibility to moisture.
Power dissipation in a prior art BGA package is limited to 3 watts or less because the heat generated by the semiconductor die is conducted from the back of the IC through the package substrate to the external PCB. Solder balls under the IC can be used to enhance power dissipation. However, to achieve power dissipation through the solder balls, the external PCB is required to have ground planes, which limit signal routing space on the PCB and increase board cost.
Further, the operating frequency--a measure of electrical performance--of a prior art BGA package is much lower than 50 MHz. The low electrical performance is due to the high inductance traces looping from the top surface of the substrate to the edge of the substrate, and then to the back-side for connecting to the solder balls. This looping of traces is dictated by current PCB technology which cannot produce fine enough lines to route traces between ball pads and by the need to electroplate the traces, which is accomplished by connecting the substrate to plating bars on the perimeter of the package.
The moisture susceptibility in a prior art BGA package is higher than a conventional plastic molded package because the PCB substrate of the BGA package absorbs more moisture and cracks the package during the board assembly process. This is because, during a high temperature step (typically greater than 200.degree. C.) in the assembly of the BGA package to an external PCB board, moisture trapped in such package during and after BGA package assembly rapidly expands. Such expansion can cause cracks on the molding, commonly known as "popcorning", thereby causing a package failure. To minimize moisture entering the BGA package prior to assembly to the external PCB board, board assembly is preferably carried out within a few hours after the BGA package is removed from a moisture-proof shipping bag.
The electrical performance and thermal dissipation of a BGA package can be considerably enhanced at a significantly increased cost by a "cavity down" BGA package. A "cavity down" BGA package uses a multilayer PCB substrate with a cavity which allows for lower electrical parasitic impedances. Such a package extends the electrical performance up to about 100 MHz. The inclusion of a solid metal slug at the bottom of the cavity increases thermal dissipation to 25 watt. The "cavity down" BGA package technology is very similar to the well-established Printed Circuit Pin Grid Array (PCPGA) technology, except that the pins of a PCPGA package are replaced in the BGA package with solder balls. The main drawback of a BGA package is the high cost.
Both "cavity up" and "cavity down" BGA packages use wire bonds to electrically connect the die to the substrate. Wire-bonding limits how fine the pad pitch can be on an IC, which in turn increases the die size of the IC, especially when the die is pad-limited. Pad-limited ICs occur more often as circuit density increases and typical die sizes reach 10.times.10 mm. A larger die size results in a higher cost, which can be avoided only by reducing the wire bond pitch. Current wire bond pitch seems to have reached its limit at 100 microns.